发明名称 |
Clock data recovery circuitry associated with programmable logic device circuitry |
摘要 |
A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system.
|
申请公布号 |
US7333570(B2) |
申请公布日期 |
2008.02.19 |
申请号 |
US20030454731 |
申请日期 |
2003.06.03 |
申请人 |
ALTERA CORPORATION |
发明人 |
AUNG EDWARD;LUI HENRY;BUTLER PAUL;TURNER JOHN;PATEL RAKESH;LEE CHONG |
分类号 |
H04L27/00;G11C7/22;H03K19/177;H03L7/07;H03L7/08;H03L7/081;H03L7/089;H03L7/099;H03L7/187;H03L7/199;H03M9/00;H04L7/02;H04L7/033 |
主分类号 |
H04L27/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|