Methods and Apparatus For Quarter-Pel Refinement In A SIMD Array Processor

摘要

An apparatus and a method for quarter-pel motion compensated search are described in the context of an array processor with tightly coupled, multi-cycle hardware assist attached to each node. A quarter-pel motion compensated search (QPMCS) instruction initiates the quarter-pel motion compensated search pipeline operation. An instruction decode and instruction operation control unit generates a starting address for a 4x4 block of a current macro block search operation indicating where to fetch the pel values. An interpolation unit determines at least eight neighboring quarter-pels per pipeline stage based on the 4x4 block of pel values. An absolute value of difference function computes the absolute value of difference values between a current macro block pel and the at least eight neighboring quarter-pels per pipeline stage. An accumulator accumulates at least eight summation values for the 4x4 block at quarter-pel positions per pipeline stage.