| 摘要 |
<p>A display for receiving m-bit display data has a display driver including a switched capacitor digital/analogue converter having an n-bit input, where m is not greater than n. The upper plates of the capacitors (C<SUB>1</SUB>... C<SUB>n-1</SUB>) of the switched capacitor digital/analogue converter may be connected, in the zeroing phase, to one of a plurality of reference voltages (V<SUB>11</SUB>, V<SUB>12</SUB>). The choice of which reference voltage is connected to the upper plates of the capacitors of the switched capacitor digital/analogue converter in the zeroing phase is independent of the input n-bit digital code, and is determined by a signal internal to the display. The output voltage range from the converter in a decoding phase may be a first range (25) in which output voltages are above and below one reference voltage (V<SUB>11</SUB>) or it may be a second range (26) in which output voltages are above and below another reference voltage (V<SUB>12</SUB>), depending on which reference voltage was selected in the preceding zeroing phase.</p> |
