PLL CIRCUIT AND METHOD FOR CONTROLLING THE SAME

摘要

A PLL(Phase Locked Loop) circuit and a method for controlling the same are provided to perform phase locking operation of a clock stably by generating an output clock using a bias voltage generated by buffering a control voltage outputted from a low pass filter. A buffer(30) generates a bias voltage by buffering a control voltage outputted from a low pass filter(20). A voltage controlled oscillator(40) oscillates an output clock by receiving the bias voltage. The buffer includes a comparison part and a voltage generation part. The comparison part generates a comparison voltage by comparing the control voltage with the fed-back bias voltage. The voltage generation part controls potential level of the bias voltage according to the potential level of the control voltage, the bias voltage and the comparison voltage.