| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem with the calculation of the source voltage fluctuation of a semiconductor memory whose capacity is increased wherein a very large amount of data is required, resulting in very large amounts of computer resources such as CPU time, memory capacity, disk capacity, etc. SOLUTION: This method for verifying layout uses a simple model consisting only of a row decoder and a column decoder for which a memory array has been selected, and a mat. A reduced netlist is created out of the simple model and a current waveform is calculated to simulate the source voltage fluctuation. By making the memory array into a simple model, computer resources such as CPU time, memory capacity, disk capacity, etc., can be greatly reduced. COPYRIGHT: (C)2008,JPO&INPIT
|
