STRUCTURE FOR POWER-EFFICIENT CACHE MEMORY

摘要

A design structure for a cache memory system ( 200 ) having a cache memory ( 204 ) partitioned into a number of banks, or "ways" ( 204 A, 204 B). The memory system includes a power controller ( 244 ) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address ( 232 ) coming into the memory system.