| 摘要 |
PROBLEM TO BE SOLVED: To provide an A/D converter which can be made inexpensive by reducing chip occupation area by decreasing the number of passive elements without causing an increase in power consumption. SOLUTION: The A/D converter has: a conversion section equipped with a plurality of cascaded conversion stages each having a quantizer quantizing each of m (n<m<2n) analog signals representing an n-dimensional vector into one or more bits to generate m parallel quantized signals, a decoder decoding the m parallel quantized signals respectively to generate m decoded analog signals, and a residue amplifier multiplying differences between the m analog signals and the m decoded analog signals by a constant to output m amplified residue signals; and a composition section which puts together the m parallel quantized signals of the respective conversion stages of the conversion section by parallel positions while taking delay quantities corresponding to cascading positions of the conversion stages into consideration. COPYRIGHT: (C)2008,JPO&INPIT
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