发明名称 SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
摘要 An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.
申请公布号 US2008038879(A1) 申请公布日期 2008.02.14
申请号 US20070877229 申请日期 2007.10.23
申请人 SIDENSE CORPORATION 发明人 KURJANOWICZ WLODEK
分类号 H01L21/82;G11C11/40;G11C11/401;G11C17/16;H01L21/28;H01L21/331;H01L21/336;H01L23/525;H01L27/10;H01L27/115;H01L29/423;H01L29/66;H01L29/78 主分类号 H01L21/82
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