| 摘要 |
A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns is disclosed. Simulation to obtain an image log-slope (ILS), normalized image log-slope (NILS), or any other characteristic of an image quality on edges of polygons in the circuit pattern obtained from circuit pattern data is performed. Properly printed edges and not-properly printed edges are identified according to a criterion of an ILS level. The original circuit pattern is separated into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
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