| 摘要 |
An increased area of an element transistor to be evaluated causes an increased leakage current due to a tunnel effect, leading to a reduced accuracy in predicting a TDDB lifetime. A test element group (TEG) 1 is a pattern for evaluating electric characteristics, comprising a plurality of unit transistors T 11 , T 12 , T 13 , T 21 , T 22 , T 23 , T 31 , T 32 , T 33 , which are arranged so as to form a lattice-shaped pattern. Each of the unit transistors comprises a gate dielectric serving as an object to be evaluated, and source region and drain region, which are a short-circuited.
|
