发明名称 CACHE MEMORY CONTROL METHOD AND DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technology for attaining high hit ratio and effective usage of cache memory. SOLUTION: A tag address is stored in first and third fields 51a and 51c which form a cache address 51. Only index address or line address together with that are stored in a second field 51b. The index address and line address are stored in a fourth field 51d. For the case of read request, the tag addresses in the first and third fields 51a and 51c are outputted to an address comparator 54, and the index address and line address stored in the second field 51b and fourth field 51d are extracted by an index address selector 56 depending on a block type selection signal, and are outputted to a tag section 52 and a data selector 55 respectively. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008033688(A) 申请公布日期 2008.02.14
申请号 JP20060207076 申请日期 2006.07.28
申请人 FUJITSU LTD 发明人 HINO MITSUAKI
分类号 G06F12/08 主分类号 G06F12/08
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