| 摘要 |
<p>A method for manufacturing a flash memory device is provided to increase program speed and to reduce threshold voltage distribution by reducing an interference gap between floating gates. A screen oxide layer, a nitride layer, and a hard mask layer which are stacked on an upper portion of a semiconductor substrate(100) and a part of the semiconductor substrate are etched to form a trench. A first dielectric is gap-filled in the trench to form an isolation layer(106), and the nitride layer and the screen oxide layer are removed. After partially etching a lateral side of the isolation layer exposed by a wet etching process, a tunnel oxide layer(108) and a first poly silicon layer(110) are formed on an upper portion of an active region of the semiconductor substrate. After a first polishing process is performed to expose an upper portion of the isolation layer, a second dielectric pattern is formed on the upper portion of the isolation layer. After a second poly silicon layer(116) is formed on an upper portion of the resultant structure, a second polishing process is performed to expose an upper portion of the second dielectric pattern. After the second dielectric pattern is removed, a dielectric(118) and a conductive layer(120) for a control gate are formed on an upper portion of the resultant structure.</p> |
