发明名称 INTERFACE MODULE AND METHOD FOR DATA COMMUNICATION BY SYNCHRONIZING CLOCK
摘要 An interface module and a method for synchronizing clock signals and transmitting and receiving data are provided to transmit and receive a control signal between components of the interface module in synchronization with operating clock signals of the components and stabilize data signals when the interface module exchanges the data signals in a slave mode. An interface module includes a transmission controller(211) and a transfer unit(240). The transmission controller operates in response to a first clock signal and outputs data inputted from a central processing unit. The transfer unit operates in response to a second clock signal and sequentially outputs data inputted from the transmission controller to a peripheral device. The transmission controller and the transfer unit respectively include synchronization units(411,241) for converting a control signal transmitted and received between the transmission controller and the transfer unit according to operating clock signals of the transmission controller and the transfer unit.
申请公布号 KR20080013548(A) 申请公布日期 2008.02.13
申请号 KR20060075219 申请日期 2006.08.09
申请人 MTEK VISION CO., LTD. 发明人 KIM, SEOK IN
分类号 G06F1/12;G06F13/14;G06F13/42 主分类号 G06F1/12
代理机构 代理人
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