NAND FLASH MEMORY DEVICE WITH 3-DIMENSIONALLY ARRANGED MEMORY CELL TRANSISTORS

摘要

A NAND flash memory device including three-dimensionally arranged memory cell transistors is provided to decrease the number of decoding circuits for selecting a wordline or select lines by making select lines or an x-th wordline in each semiconductor layer have equipotential. Stacked L semiconductor layers(100,200) are formed, wherein L is an integer greater than 1. A string select line(SSL(1),SSL(2)), a ground select line(GSL(1),GSL(2)) and M wordlines disposed between the string select line and the ground select line are formed, wherein M is an integer greater than 1. L gate structures are disposed on the semiconductor layer, respectively. N bitlines are disposed on the gate structures wherein N is an integer greater than 1, and cross the string select line, the ground select line and the wordlines. Common source lines(CSL(1),CSL(2)) are disposed on each semiconductor layer and are mutually interconnected to form an equipotential. The string select lines disposed on each semiconductor layer are mutually interconnected to form an equipotential. The ground select lines disposed on each semiconductor layer are mutually interconnected to form an equipotential.