| 摘要 |
The invention relates to a digital synchronization network, and provides a DPLL circuit having a holdover function that generates a high-precision reference clock with a temperature correction to perform a free-running frequency control at a holdover time. In a holdover mode of the DPLL circuit using a DDS, the DPLL circuit having a holdover function adds a correction value calculated from a temperature characteristic of a slave oscillator to a fixed DDS control value during a detection of a holdover, thereby changing the DDS control value according to the temperature characteristic.
|
