| 摘要 |
A semiconductor memory device is provided to select an optimal refresh timing by establishing operation timing efficiently through testing RAS timing. A semiconductor memory device comprises a bank(500), an input buffer part(100), an RAS timing control part(400) and a bank control part(300). The input buffer part receives and transfers an RAS timing test signal. The RAS timing control part generates an RAS timing signal. The bank control part controls refresh operation timing of the bank in response to the RAS timing test signal outputted from the input buffer part in a test mode, and controls refresh operation timing of the bank in response to the RAS timing signal in a normal mode.
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