| 摘要 |
An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status indicating signal received through an interrupt status indicating pin of a north bridge module or by the triggering of a peripheral device coupled to the south bridge chip, the PIC sends an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode. The APIC is disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a memory write cycle message to the CPU in response to the triggering of the peripheral device. The power management unit is optionally triggered with the interrupt signal or the interrupt status indicating signal to awake the CPU.
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