| 摘要 |
An overlay vernier of a semiconductor device is provided to avoid damage to an overlay vernier by including a first overlay vernier having a predetermined number of overlay vernier division patterns arranged in one direction and by including a second overlay vernier having a predetermined number of overlay vernier division patterns arranged in a direction perpendicular to the arrangement direction of the first overlay vernier. A predetermined number of overlay vernier division patterns(125) are arranged in one direction of a first overlay vernier(130) of a square shape wherein a main scale(100) of a bar type and a vernier scale(120) of a bar type are interconnected at their ends of a lengthwise direction. A predetermined number of overlay vernier division patterns are arranged in a direction perpendicular to the one direction in a second overlay vernier(140) of a square shape. The main scale is made of a concave part with a predetermined step. The vernier scale is made of a concave part with a predetermined step.
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