VERTICAL TYPE STACKED MULTI-CHIP PACKAGE IMPROVING A RELIABILITY OF A LOWER SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME

摘要

A vertically stacked multi chip package with improved reliability of a lower semiconductor chip is provided to overcome a difficulty of wire bonding caused by overhang by additionally forming a metal stiffener on a first semiconductor package. A printed circuit pattern on which a semiconductor chip is mounted is formed in an organic substrate(102). A first semiconductor chip(106) is mounted on a die attach region of the organic substrate, electrically connected to the organic substrate by a first wire(108). A metal stiffener is formed on the first semiconductor chip, connected to the organic substrate in the outer portion of the first semiconductor chip by a first ground unit. Encapsulant(116) encapsulates the first semiconductor chip under the metal stiffener. A second semiconductor chip(118) is mounted on the metal stiffener, connected to the metal stiffener by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire(120), greater than the first semiconductor chip. The lower portion of the resultant structure on the organic substrate and the second semiconductor chip are sealed by encapsulation resin. A solder ball is attached to a solder ball pad under the organic substrate. The printed circuit pattern of the organic substrate includes a solder bump(110) for connecting the metal stiffener.