| 摘要 |
<p>A method for forming a dual poly gate of a semiconductor device is provided to increase a threshold voltage and to improve device property and reliability by forming a high concentration P+ poly silicon layer at a recessed substrate in a cell region. A gate dielectric(110) is formed on the semiconductor substrate(100) divided into a cell region and a peripheral region including a PMOS and an NMOS forming regions. A first undoped polysilicon layer with a uniform thickness is formed on the gate dielectric. Germanium ion is selectively ion-implanted into the first poly silicon layer of the cell region and the PMOS forming region of the peripheral region. A P-type impurity is selectively ion-implanted into the first polysilicon layer of the cell region and the PMOS forming region of the peripheral region on which the germanium ion is implanted. A second polysilicon layer(140) on which P-type impurity is implanted with a low concentration, is formed on the first polysilicon layer on which the P type impurity is partially ion-implanted. An N-type impurity is selectively ion-implanted with a high concentration into the second and first polysilicon layers of the NMOS region of the peripheral region. A metal-based layer(160) and a hard mask layer(170) are formed in turn on the second polysilicon layer. The hard mask layer, the metal-based layer, the second polysilicon layer, the first polysilicon layer, and the gate dielectric are etched.</p> |
