发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for preventing upsizing due to provision of a fault position analysis circuit. SOLUTION: The semiconductor integrated circuit device comprises: scan path circuits SC1-SCn provided corresponding to storage sections RM1-RMn in a one-to-one relationship; an OR circuit OR1 for performing OR operation by receiving serial data SO1-SOn outputted from the scan path circuits SC1-SCn; and the fault position analysis circuit ENC for receiving OR operation output. In the fault position analysis circuit ENC, fault position information FAIL_POSI and a fail flag FAIL_FLAG are outputted based on the OR operation output. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008021359(A) 申请公布日期 2008.01.31
申请号 JP20060191362 申请日期 2006.07.12
申请人 RENESAS TECHNOLOGY CORP 发明人 MAENO HIDESHI
分类号 G11C29/34;G01R31/28 主分类号 G11C29/34
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