| 摘要 |
In some embodiments, when etching a dielectric to form a self-aligned contact opening to a source/drain region ( 160 ) of a transistor, the gate structure ( 220 ) is protected on top with a non-conformal layer (M 3 ), possibly silicon, deposited so that it is thicker over the gate than over the source/drain region. The silicon may be insulated from the gates by another dielectric layer (M 2 ). When the non-conformal layer is etched over the source/drain region, it may also be etched on top of the gate structure, but the gate structure remains protected due to the greater thickness of the non-conformal layer.
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