| 摘要 |
An integrator is provided with protection against drift in the value of an integral during power save mode. An N-bit counter ( 12 ) is driven by the output of a comparator ( 11 ) to provide a digital count representation of the integral. The digital count is fed as an input to a current-steering digital-to-analog converter ( 14 ) which provides a current of corresponding analog magnitude to other circuitry, such as to an input stage of an error amplifier. The digital count is maintained during power save mode, preserving the integral value until resumption of normal operation.
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