| 摘要 |
PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of effectively accessing a synchronous DRAM. SOLUTION: The synchronous DRAM has four banks. A logical address 90 has a row address part 91 and a column address part 92 of the upper side 90a and a bank bit part 93 of lower two bits. A memory controller accesses each minimum access unit specified by the logical address 90. Thereby, when continuous logical addresses 90 are specified and respective minimum access units are successively accessed, the memory controller switches banks for every access. Thereby, even in a precharged period of one bank, data can be read out from the minimum access unit in the other bank. COPYRIGHT: (C)2008,JPO&INPIT
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