| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DLL circuit in which phase comparison is performed between a value smoothing a first clock output through an LPF and a second clock signal delaying a first clock signal, and a value smoothing the output of a clock signal frequency-dividing an edge of an UP/DN signal, as an output result of a phase comparator, into 1/2 is adjusted through negative feedback control using an operational amplifier. <P>SOLUTION: A first voltage value smoothing a first clock signal PH0 through an LPF 20 and a second voltage value detecting an edge of a phase compared output signal and smoothing a signal frequency-dividing a signal ORing out a detection result into 1/2 through an LPF 21 are inputted to an operational amplifier 22, and a charging/discharging current is regulated with an output voltage of the operational amplifier 22 so that the first and second smoothed voltages become equal. <P>COPYRIGHT: (C)2008,JPO&INPIT |
