发明名称 Nonlinear Receiver Model For Gate-Level Delay Calculation
摘要 A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity.
申请公布号 US2008028350(A1) 申请公布日期 2008.01.31
申请号 US20070866981 申请日期 2007.10.03
申请人 SYNOPSYS, INC. 发明人 LEVY HAROLD J.
分类号 G06F17/50 主分类号 G06F17/50
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