发明名称 Method and System for Handling Process Related Variations for Integrated Circuits Based Upon Reflections
摘要 Disclosed is an approach for modeling and correcting for the effects of reflections during lithography processing. Thickness differences across the surfaces in different integrated circuit layers may result in reflectance-related variations. The variations may be modeled and accounted for during the design process for the integrated circuit.
申请公布号 US2008027698(A1) 申请公布日期 2008.01.31
申请号 US20070768891 申请日期 2007.06.26
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 WHITE DAVID
分类号 G06F17/50 主分类号 G06F17/50
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