ACTIVELY COMPENSATED BUFFERING FOR HIGH SPEED CURRENT MODE LOGIC DATA PATH

摘要

An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.