| 摘要 |
The present invention uses a Direct Memory Access controller for controlling DMA transfer for a plurality of channels whose priorities are set respectively and receives Data Request Signals for requesting data transfer for the respective channels. The DMA controller executes the DMA transfer for a channel having the highest priority from among the DMA transfer corresponding to the channels that receive the Data Request Signals. The DMA controller sets the priority of a channel used for the DMA transfer to the lowest priority. The DMA controller sets the priorities of other channels used for the DMA transfer to priorities when the DMA transfer is executed or the priorities different therefrom, which are predetermined priority other than the lowest priority.
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