| 摘要 |
The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.
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