发明名称 A/D CONVERTER AND DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To improve performance of a data processor provided with an A/D converter. SOLUTION: The A/D converter includes a data register (221), an A/D conversion value addition mode selecting register (202), and an A/D conversion control circuit (222) for controlling the A/D converter (208) to continuously execute for a plurality of times the A/D conversion of the same analog signal when the A/D conversion value addition mode is set to the A/D conversion value addition mode selecting register and storing a sum of such conversion values to the data register. In the data processor including such A/D converter, improvement in the performance is possible, because it is not required to execute the summing average processing of the A/D conversion result after an output data of data register in the A/D converter is extracted. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008022387(A) 申请公布日期 2008.01.31
申请号 JP20060193503 申请日期 2006.07.14
申请人 RENESAS TECHNOLOGY CORP 发明人 TSUNAKAWA HIROYUKI;YADA NAOKI
分类号 H03M1/12;G06F3/05 主分类号 H03M1/12
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