| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an information processor capable of rapidly detecting an error in data read and rapidly transferring data without any error. <P>SOLUTION: A navigation system program and precalculated error detection codes are stored in a boot device 13. When starting a navigation device 1, a CPU 11 reads the navigation system program from the boot device 13 and stores it in an SDRAM 12. At this time, an FPGA 14 which is hardware different from the CPU 11 incorporates data of the navigation system program synchronously with reading of the navigation system program from the boot device 13, and computes error detection codes. When the CPU 11 completes reading of the navigation system program, the error detection codes computed by the FPGA 14 are compared with the error detection codes stored beforehand in the boot device 13, to determine whether an error is in reading of the navigation system program from the boot device 13. <P>COPYRIGHT: (C)2008,JPO&INPIT |
