发明名称 BUFFER FLOW CONTROLLER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a buffer flow controller which can reduce a processing load and power consumption accompanied by the change of a frequency. <P>SOLUTION: A sampling part 6 samples data inputted at a second frequency to a first frequency of a standard value set in advance and outputs it to a writing part 2. The writing part 2 writes the input data into a buffer memory 1. A reading part 3 reads the data from the buffer memory 1. When a data quantity of the buffer memory 1 is not within a prescribed range, a control part 5 changes the first frequency of the sampling part to a maximum value or a minimum value fixed in advance. When the first frequency is the maximum value or the minimum value, the standard value is updated so that the switching period of the frequency may become long. Consequently, the processing load and power consumption accompanied by the change of the frequency can be reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008022450(A) 申请公布日期 2008.01.31
申请号 JP20060194195 申请日期 2006.07.14
申请人 MEGACHIPS LSI SOLUTIONS INC 发明人 MATSUTANI TAKASHI;IMAI YUJI
分类号 H04L13/08;H04L7/00 主分类号 H04L13/08
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