| 摘要 |
A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.
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