发明名称 Systolic array
摘要 Disclosed is a one-dimensional MFA systolic array for matrix computation using an MFA (modified Faddeeva algorithm), in which downward square MFA array processing and upward square MFA array processing are mapped to a one-dimensional array in horizontal directions, respectively. In each PE in the one-dimensional array, downward and upward MFA matrix calculations for two threads are executed. An input and an output are provided for each of PEs at both ends of the one-dimensional array.
申请公布号 US2008028015(A1) 申请公布日期 2008.01.31
申请号 US20070878058 申请日期 2007.07.20
申请人 NEC ELECTRONICS CORPORATION 发明人 SEKI KATSUTOSHI
分类号 G06F7/32 主分类号 G06F7/32
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