| 摘要 |
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over the columns that the capacitors service. The number of pairs provided in the vertical stack is subject to optimization, and for a given set of design constraints, a certain form factors can prove to be optimal. No modification needs to be made to the pixel array (such as pixel pitch), and the sensing circuitry otherwise requires no electrical or process modifications as the values for the capacitances as well as other design constraint are preserved. However, the vertical stacking of the plurality of pairs of capacitors reduces the overall column height (CH), which conserves layout space on the CMOS imager integrated circuit.
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