| 摘要 |
<p>A feedback circuit part (150) comprises a third variable delayer (153) that can vary the delay amount of the phase of a first input clock fp (ft); a third logic gate (163) that determines a phase difference between an output ft2 delayed by the third variable delayer (153) and the first input clock ft and outputs a third output signal tst having a pulse width corresponding to the phase difference; and an LPF (173) that outputs, as a control signal Vcontrol, a value obtained by integrating the pulse width of the third output signal tst outputted by the third logic gate (163). The control signal Vcontrol outputted by the LPF (173) is fed back to the third variable delayer (153) as a delay amount thereof, and further outputted as the delay amounts of first and second variable delayers (111,112) of a phase difference determining part (110).</p> |
