发明名称 POWER MANAGEMENT IN A DATA PROCESSING DEVICE HAVING MASTERS AND SLAVES
摘要 <p>A device (2), such as an integrated circuit is described including master units (8, 10) and slave units (6, 18, 20) connected by an interconnect (14). In addition to the normal data signals (22) and address signals (24) passed with a transaction, there are also passed usage signals (26) which specify the time interval until a next transaction will be sent to a slave unit. A local slave power controller (34) is responsive to such usage signals (26) to switch into a low power mode and pre-emptively switch back to an operational mode in time to respond to the next transaction to be received.</p>
申请公布号 WO2008012483(A1) 申请公布日期 2008.01.31
申请号 WO2006GB02830 申请日期 2006.07.28
申请人 ARM LIMITED;TUNE, ANDREW 发明人 TUNE, ANDREW
分类号 G06F1/32 主分类号 G06F1/32
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