发明名称 |
BUILT IN SELF TEST AND BUILT IN SELF REPAIR SYSTEM |
摘要 |
A RAM test and fail repair system is provided to test a RAM with an automatically generated test pattern by adding a BIST(Built In Self Test) and a BISR(Built In Self Repair) circuit in a device and to repair fail bits into normal bits. According to a RAM(Random Access Memory) test and fail repair system, a first operating part(100) includes a RAM(110), an internal register(120) and a fail treatment part(130). The RAM comprises a main RAM and a redundancy cell. The internal register stores a fail address and a good redundancy address. The fail treatment part stores fail address and good redundancy address in the internal register by comparing a test pattern written in the RAM with a test pattern through an internal comparator. A second operating part(200) comprises a RAM address counter(210) generated addresses to access a RAM cell and a comparator(220) comparing the address generated in the RAM address counter with a fail address.
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申请公布号 |
KR20080010868(A) |
申请公布日期 |
2008.01.31 |
申请号 |
KR20060071523 |
申请日期 |
2006.07.28 |
申请人 |
TOMATO LSI INC. |
发明人 |
CHEON, JAE IL;JEONG, DUK JU;LEE, YONG WOON |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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