发明名称 |
Evaluation method using a TEG, a method of manufacturing a semiconductor device having the TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recording the program |
摘要 |
The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several mum interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.
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申请公布号 |
US2008026490(A1) |
申请公布日期 |
2008.01.31 |
申请号 |
US20070826861 |
申请日期 |
2007.07.19 |
申请人 |
ASANO ETSUKO;NAKAMURA OSAMU;SAKAKURA MASAYUKI |
发明人 |
ASANO ETSUKO;NAKAMURA OSAMU;SAKAKURA MASAYUKI |
分类号 |
H01L21/66;H01L21/00 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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