| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit for accurately discriminating whether a synchronous clock signal whose duty ratio is required can be generated or not. <P>SOLUTION: A clock generation circuit 100 is provided with: a DLL circuit 110 for generating a synchronous clock signal Sclk synchronized with an external clock signal Sextclk by delaying the external clock signal Sextclk inputted from the outside; a test signal generation circuit 120 for generating a test signal Stest whose pulse width is changed for the duty ratio deterioration test of the DLL circuit 110; and a selection circuit 130 for selecting either the external clock signal Sextclk or the test signal Stest, and for inputting the signal to the DLL circuit 110. <P>COPYRIGHT: (C)2008,JPO&INPIT |
