| 摘要 |
A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.
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