发明名称 |
METHOD FOR FORMING A STRAINED TRANSISTOR BY STRESS MEMORIZATION BASED ON A STRESSED IMPLANTATION MASK |
摘要 |
By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.
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申请公布号 |
US2008026572(A1) |
申请公布日期 |
2008.01.31 |
申请号 |
US20070746106 |
申请日期 |
2007.05.09 |
申请人 |
WIRBELEIT FRANK;BOSCHKE ROMAN;GERHARDT MARTIN |
发明人 |
WIRBELEIT FRANK;BOSCHKE ROMAN;GERHARDT MARTIN |
分类号 |
H01L21/44 |
主分类号 |
H01L21/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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