Fast dynamic CMOS flip-flops and gates

摘要

In a dynamic CMOS flip-flop the node N1911 is first precharged by PMOS 1911 under control of the clock signal CK2 and then selectively discharged in dependence on the input D when the narrow clock pulse CKP is asserted. If the node N1911 remains high then node N1931 is discharged when CKP is asserted, but if the node N1911 is pulled low then the node N1931 is pulled high by PMOS 1931. The latches 1920 and 1940 maintain the voltages on nodes N1911 and N1931 when the nodes are not otherwise driven. The devices 1922 and 1923 are optional (see figure 20) and prevent contention between the latch 1920 and the input branch 1911,1912,1913.