发明名称 Soft core control of dedicated memory interface hardware in a programmable logic device
摘要 The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
申请公布号 US7323903(B1) 申请公布日期 2008.01.29
申请号 US20060530708 申请日期 2006.09.11
申请人 发明人
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
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