发明名称 |
PLL circuit with deadlock detection circuit |
摘要 |
Disclosed is a PLL circuit including a deadlock detection circuit includes a counter circuit for counting a clock signal. In a deadlock state, the deadlock detection circuit outputs a deadlock detection signal responsive to an output signal from the counter circuit when the counter circuit has counted a preset number of the clock signal. The deadlock detection signal serves to release the PLL circuit from the dead lock. During the normal operation, the counter circuit does not impart noise to the PLL circuit.
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申请公布号 |
US7323943(B2) |
申请公布日期 |
2008.01.29 |
申请号 |
US20050280169 |
申请日期 |
2005.11.17 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
KANEKO MAKOTO;NAKAMURA SATOSHI |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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