CIRCUIT ARRANGEMENT

摘要

The invention relates to a circuit arrangement comprising: a functional circuit with m (m = 1, 2,...) data inputs and n (n = 1, 2,...) data outputs for processing at least one m-dimensional binary data input (x1,..., xm) to form an n-dimensional data output (y1,..., yn), where the functional circuit comprises at least one combinatorial circuit part; at least two registers with a word length k (k = 1, 2,...; k = n), which are coupled to at least some of the n data outputs of the functional circuit in order to store output values (y = y1,..., yk; y' = y'1,..., y'k), derived from the n-dimensional data output (y1,..., yn) of the functional circuit, said values being duplicated in respect of one another or duplicated with bit-by-bit inversion in respect of one another; at least one corrector with an input word length 2k and an output word length k, which is coupled to data outputs of the at least two registers and supplies a k-dimensional corrected data output (y (corr) = y1 (corr),..., yk(corr)); and an error recognition circuit for error recognition in the course of operation of at least one of the aforementioned circuit elements - the functional circuit, the at least two registers and the corrector.