发明名称 LEVEL CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide a level converter which is capable of determining an initial value of a latch circuit and has excellent symmetry in rising/falling characteristics of an output signal. SOLUTION: MOS transistors Tp3, Tp4 for initial value setting are inserted and connected between nodes N1, N2 that become output terminals of first and second inverters 32, 33 constituting a latch circuit 31 of a shift circuit 12 and transistors Tp1, Tp2. A gate of the MOS transistor Tp3 is then connected to a ground and a gate of the MOS transistor Tp4 is connected to an initial value setting circuit 34. The initial value setting circuit 34 controls a gate potential of the MOS transistor Tp4 to an intermediate potential between a second high potential power source VDE and the ground when the second high potential power source VDE is below a predetermined level, and controls the gate potential to a ground level so as to turn on the MOS transistor Tp4 when the second high potential power source VDE is above the predetermined level. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008017456(A) 申请公布日期 2008.01.24
申请号 JP20070135675 申请日期 2007.05.22
申请人 FUJITSU LTD 发明人 KOTO TOMOHIKO
分类号 H03K19/0185 主分类号 H03K19/0185
代理机构 代理人
主权项
地址
您可能感兴趣的专利