| 摘要 |
A clock converting circuit ( 1 ) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(fxm) to n-phase clocks of the frequency f having a phase difference of 1/(fxn). A single-phase clock generating circuit ( 2 ) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(fxn) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit ( 1 ) is 'f', if a desired frequency of the single-phase clocks is decided, then 'n' can be obtained from the equation: the frequency of the single-phase clocks is equal to (fxn). This value of 'n' is set to the clock converting circuit ( 1 ), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.
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