发明名称 CIRCUIT, SYSTEM AND METHOD FOR PROCESSING IMAGE
摘要 <p><P>PROBLEM TO BE SOLVED: To shorten line switching wait time in processing pixel data for each line. <P>SOLUTION: Each function block constituting a pipeline resets its own storage element in synchronization with the timing to process and output pixel data at the end of one line. A reset control unit 123 of a head function block 120 includes an attribute signal generation circuit 126 generating attribute signals indicating whether or not each pixel data to be inputted is the pixel data at the end, and transfers the attribute signals by synchronizing them with corresponding pixel data so as to be made attached thereto. When the processed pixel data is outputted, the control unit 123 controls the reset of the storage elements with reference to the attribute signals of the pixel data. Other function blocks control the reset of their own storage elements by using the attribute signals transferred from the precedent function block in synchronization with the pixel data. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008015565(A) 申请公布日期 2008.01.24
申请号 JP20060182808 申请日期 2006.06.30
申请人 NEC ELECTRONICS CORP 发明人 WASEDA RYUJI
分类号 G06T1/20;G06T1/60 主分类号 G06T1/20
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